1. Technical Field
The present invention relates to a memory device, and more particularly, to a non-volatile memory device and a method of driving the same.
2. Discussion of the Related Art
Flash memory is a widely used form of non-volatile memory. Flash memory has short access times like a storage medium based on a magnetic disk, such as a hard disk, but consumes less power.
Flash memory can be classified as a NOR type or a NAND type according to the connection state between cells and bit lines of the flash memory. NOR type flash memory is configured such that two or more cell transistors are connected to one bit line in parallel. NOR type flash memory stores data using channel hot electrons and erases data using Fowler-Nordheim (F-N) tunneling. NAND type flash memory is configured such that two or more cell transistors are connected to one bit line in series. NAND type flash memory writes and erases data using the F-N tunneling. Although NOR type flash memory uses a relatively large amount of cell current, it can function at relatively high speeds. NAND type flash memory uses a small amount of cell current and is thus particularly suited for highly-integrated devices.
FIG. 1A is a circuit diagram of a memory cell included in a general NAND type flash memory. In FIG. 1A, a plurality of word lines WL11 to WL14 and a plurality of memory cells M11 to M14 are illustrated, and the plurality of memory cells M11 to M14 form a string with selective transistors ST1 and ST2 and are connected in series between a bit line BL and a ground voltage VSS. Since NAND type flash memory uses a relatively small amount of cell current, programming for all memory cells connected to a single word line (for example, WL11 to WL14) may be performed through a single program operation.
FIG. 1B is a circuit diagram of a memory cell included in a general NOR type flash memory. As illustrated in FIG. 1B, memory cells M21 to M26 are connected between a bit line BL1 or BL2 and a source line CSL. Since the NOR type flash memory consumes a relatively large amount of cell current during a program operation, only a predetermined number of memory cells may be programmed during a single program operation.
In general, a memory cell array included in a memory device includes a main cell for storing data and a redundancy cell that may substitute for a defective cell of the main cell if the main cell has a defect. The memory cell may also include a fuse circuit for storing an address of the defective cell, i.e., a defect address. The fuse circuit checks if a provided address corresponds to the address of the defective cell and replaces the address of the defective cell with an address corresponding to the redundancy cell.
The fuse circuit stores information for setting the operating environment of the memory device when the memory device is powered on and also stores address information for repairing the defective cell in the manner discussed above. The information for setting the operating environment of the memory cell may comprise initial setting data and may include data for controlling a direct current (DC) voltage associated with an operation of the memory device such as a program operation, a read operation, and an erase operation.
When the initial setting data is stored in the fuse circuit, the initial setting data that sets the operating environment is difficult to change. To improve the flexibility of the operating environment of the memory device, the initial setting data stored in the memory cell array is reprogrammed.
FIG. 2 is a block diagram of a memory cell array 10 in which page buffers and bit lines are arranged. Referring to FIG. 2, the memory cell array 10 includes at least one block (Block 0 to Block n), in which a plurality of bit lines BLe and BLo are arranged as pairs. A page buffer unit 20 includes a plurality of buffers, each of which is electrically connected to a corresponding bit-line pair. A page may be defined as a unit in which a program or read operation may be performed in a flash memory. Each page generally has a size of 512 bytes or 2K bytes.
FIG. 3 is a block diagram of a memory cell array having a redundancy cell array 40 and page buffers. Referring to FIG. 3, the memory cell array includes a main cell array 30 and the redundancy cell array 40 corresponding thereto. For example, the redundancy cell array 40 is arranged to repair a fail column in the main cell array 30.
A first buffer unit 50 including a plurality of page buffers corresponds to the main cell array 30. Each of the plurality of page buffers included in the first buffer unit 50 is electrically connected to a corresponding bit-line pair of the main cell array 30. A second buffer unit 60 including a plurality of page buffers corresponds to the redundancy cell array 40. Each of the plurality of page buffers included in the second buffer unit 60 is electrically connected to a corresponding bit-line pair of the redundancy cell array 40.
As illustrated in FIG. 3, in a plurality of bit lines arranged in the memory cell array, a fail column may be present due to a cutoff of a bit line or a short circuit between bit lines during a manufacturing process. When the fail column is present, it is replaced with a redundancy column through a repair process. In the repair process, when a memory device is powered on, a defect address stored in the main cell array 30 is read and is then stored in a predetermined region. Thereafter, if some of the addresses of columns that are input by a user during a program operation, a read operation, or an erase operation, correspond to a defect address, fail columns corresponding to the defect address are replaced with the redundancy column. In FIG. 3, during the repair process, fail columns present in the main cell array 30 are replaced with the redundancy column in units of two page buffers. Two page buffers 51 corresponding to bit lines including fail columns are replaced with two page buffers 61 corresponding to redundancy columns.
As mentioned above, once power is on, a conventional non-volatile memory device reads initial setting data stored in a memory cell array through an initial read operation and sets its operating environment according to the read setting data. However, since the initial setting data is read prior to a repair process, the initial setting data may be read from an array including a fail column. As a result, the read initial setting data may have an error and in this case, the memory device may not be set to operate in a desired mode.